Complementary field effect circuit arrangements employ an n-channel and a p-channel field effect transistor which are coupled so that the source or drain of one device is connected to the source or drain of the other device. In any mode of circuit operation, one of the devices will be functioning and the other will be off. When operating conditions within the circuit dictate that the functioning device turns off, the device which was previously off will begin to function due to interconnection of the sources and/or drains of the two devices. This concept was first disclosed by Wanlass in U.S. Pat. No. 3,356,858. It is especially useful because no additional power is required to switch either of the devices. Switching is an inherent attribute of circuit operation.
Conventional complementary field effect devices are fabricated as conductor-insulator-semiconductor structures with interconnections between particular sources or drains of the n-channel and p-channel devices. The conductors may be metal or conductive polycrystalline silicon. Silicon dioxide is the most widely used insulator and single crystal silicon is the most widely used semiconductor substrate. Typical complementary metal oxide semiconductor (CMOS) structures are fabricated on an n-type substrate rather than on a p-type substrate because it is easier to obtain desirable threshold voltages for both the n-channel and p-channel complementary devices. The p-well required for the n-channel complement is obtained by diffusing a lightly doped p-region into the n-type substrate. In some devices all n-channel devices are fabricated in a common p-well, and p-channel devices are fabricated in the n-substrate so that much of the overall area is taken up with interconnections between the n-channel and p-channel devices. Where individual p-wells are used for the n-channel devices, isolation of the p-channel field effect transistors is sometimes achieved by heavily doped channel stops. These channel stops occupy a large amount of wafer surface area, degrade operating speed and limit the voltage range. Recently, polycrystalline silicon has been used in place of metal for the gate electrodes of the devices, but although transient performance is slightly improved, a negligible reduction in area has been effected. Also, the standard dopant, boron, which is placed in the polycrystalline silicon to render it conductive and to obtain a low threshold, possesses the property that it may diffuse through the gate oxide in the presence of hydrogen and degrade the device. And, prior-art CMOS devices are known to experience impurity migration through both the gate and field oxides with resultant impairment in the operating characteristics of the devices. Finally, the presence of uncontrolled amounts of fixed surface states charges, due typically to non-stoichiometric composition of the SiO.sub.2, also impairs the operating characteristics of the devices.